In order to improve the density of the memory device, the industry has worked extensively at developing a method for reducing the size of the two-dimensional arranged memory cells. As the size of the memory cells of the two-dimensional (2D) memory devices continues to shrink, signal conflict and interference will significantly increase, so that it is difficult to perform operation of multi-level cell (MLC). In order to overcome the limitations of 2D memory device, the industry has developed a memory device having a three-dimensional (3D) structure, by way of the memory cell arranged three-dimensionally on the substrate to improve the integration density.
Specifically, a multilayer laminated structure (e.g., a plurality of ONO structures of alternating oxide and nitride) may firstly deposited on the substrate; by an anisotropic etching process for etching the multilayer laminated structure on the substrate, a plurality of channel through-holes distributed along the word line (WL) of memory cell extending direction and perpendicular to the substrate surface are formed (may extend through to the substrate surface or even with a certain over-etch); a plurality of pillar-shaped channels are formed in the channel through-holes by depositing polysilicon material; the multilayer laminated structure is etched along the WL direction to form a plurality of trenches through to the substrate, exposing the multilayer stack surrounding the pillar-shaped channels; a certain type of materials in the stack is removed by wet etching (e.g., using hot phosphoric acid to remove nitrogen silicon, or HF to remove silicon oxide), leaving a plurality of projecting structures lateral distributed around the pillar-shaped channels; a gate dielectric layer (such as high-k dielectric materials) and a gate conductive layer (e.g., Ti, W, Cu, Mo, etc.) are deposited on the side walls of the projecting structures in the trenches to form a gate stack; the portion of the gate stack above the lateral plane of the projecting structures is removed by vertical anisotropic etching until the gate dielectric layer on the side of the projecting structures is exposed; the laminated structure is etched to form a plurality of source/drain contacts, and rear end of the manufacturing processes are completed. Here, a portion of projecting structures of the laminated structure which is left on the sidewall of pillar-shaped channels forms a plurality of spacers between the gate electrodes, while the gate stacks sandwiched between the spacers form the control electrodes. When a voltage is applied to the gates, the fringe field of the gate will enable a plurality of source-drain regions to be formed on the sidewalls of pillar-shaped channels made of e.g. polysilicon material, thereby constituting a gate array composed of a plurality of series-parallel connected MOSFETs so as to record the stored logic states.
As the device size has further reduced to e.g. 22 nm, and even 10 nm mode, the resistance of channel region composed of polysilicon materials increased significantly, the method and device structure of applying a voltage to the gate to induce source-drain regions in channel region are facing the problems of reduced induction efficiency, decreased induction intensity, and increased series resistance, which directly affects the read current and read speed of memory array. In extreme cases, the potential at a node being remote from the memory cell read node (e.g., the bit line BL on the top of a stack structure or the metal silicide of source region in substrate) may be insufficient to generate inductively the source-drain regions in the channel region, thereby causing the entire memory cells fails, and the data cannot be read.